1. Field of the Invention
The disclosure relates in general to an active device and a semiconductor device with the same, and more particularly to an active device sufficient to sustain high voltage (HV) operation and a HV semiconductor device with the active device free of STI edge issue.
2. Description of the Related Art
In modern very-large-scale integration (VLSI) technology, the shallow-trench isolation (STI) is usually used to isolate the active devices (such as CMOS transistors) to define the channel width. However, it has been found that the STI edge, in many cases, has several serve issues.
FIG. 1 illustrates a conventional layout of a semiconductor device. The semiconductor device comprises several active devices 10 arranged separately from each other on a substrate and within a first well with the first conductive type, such as a P-well (PW) for the NMOS. Also, a light doping region having the second conductive type (such as N−) is correspondingly confined within the PW and encloses all of the active devices 10 and P-well contact. The adjacent active devices 10 are isolated by the STI. Each active devices 10 comprises a diffusion region DIF with the first conductive type, a first contact region 111 (such as a drain region) and a second contact region 113 (such as a source region) respectively formed in the diffusion region DIF, and a poly gate PG (having a gate contact 115 thereon) formed between the first contact region 111 and the second contact region 113. For the conventional semiconductor device, STI existing between the adjacent active devices 10 cause undesired STI edge issues.
FIG. 2 is a cross-sectional view showing the isolations besides the poly gate of a conventional semiconductor device. A poly gate PG is formed on the gate oxide GOX, and a channel 135 is formed under the poly gate PG and between the isolations STI. FIG. 3A shows the ID-VG characteristic curves of a typical low voltage (LV) NMOS transistor with 70 Å of the gate oxide (GOX=70 Å) and W/Lg=0.6 μm/0.4 μm, and the curves are measured at a drain bias VD=0.1 V. FIG. 3B shows the ID-VG characteristic curves of a typical high voltage (HV) NMOS transistor with 370 Å of the gate oxide (GOX=370 Å) and W/Lg=10 μm/1.6 μm, and the curves are measured at a drain bias VD=0.1V. Please refer to FIG. 1˜FIG. 3B. The STI edge is often a “weak point” (as circled in FIG. 2) that causes abnormal subthreshold leakage current and leads to an undesirable double hump in the subthreshold ID-VG characteristics (such as curves Process-1 in FIG. 3A and FIG. 3B). In FIG. 3A and FIG. 3B, curves Process-1 represent the ID-VG characteristic curves of the typical NMOS transistors with double hump leakage, curves Process-2 represent the ID-VG characteristic curves of the typical NMOS transistors with improved STI, and curves Process-3 represent the ID-VG characteristic curves of the typical NMOS transistors with improved STI and sidewall STI pocket implant.
Generally, the STI sidewall often has several non-ideal issues, such as: (1) boron segregation at the STI sidewall that leads to p-well dosage loss; (2) STI induced stress that affects Vt (threshold voltage) stability; and (3) some interface trap or dislocation that enhanced leakages. All these issues cause the non-ideal subthreshold behavior and higher leakage current issues. Although a sidewall STI pocket IMP is frequently applied at the “weak points” (as circled in FIG. 2) to raise the local well-doping at the STI sidewall and suppress the double-hump leakage (curves Process-3), it has drawbacks including: (1) reduced junction breakdown of HVNMOS, because junction (NM) will see more P-well doping at the STI edge; and (2) severe narrow-width effect when the channel width is scaled down. The STI pocket IMP still affects the channel doping and affects the Vt control.